1. Field of the Invention
The present invention relates to Electrostatic Discharge Protection (ESDP) devices. In particular, the present invention relates to triggering mechanisms for activating metal-oxide-silicon (MOS) transistors or bipolar transistors used as ESDP structures.
2. Description of the Prior Art
The fabrication of increasingly smaller integrated circuit (IC) devices has made the reliance upon effective smaller ESDP devices more important. It is well known that transient voltage surges, referred to as electrostatic discharges that may be thousands of volts, commonly occur at the terminals of IC""s. These terminals are electrically coupled to active circuit components including, but not limited to, bipolar and MOS transistors. It is important to block ESD events or to divert ESD events away from the gates of transistors, particularly those transistors acting as circuit buffers, in order to ensure that the transistors are not destroyed or otherwise compromised. When that occurs, operation of the circuit can be adversely affected, including the possibility of system failure.
As ESD problems are widespread, wide arrays of solutions have been developed. For the most part, these solutions have involved the placement of low-breakdown transistors or diodes in parallel with the circuit to be protected. The transistor or diode is designed to be non-conducting under expected potential values, and conducting when a potential on an input or output buffer node exceeds those expected values. When turned on by the higher-than-expected potential, the ESD device is designed to divert inordinately high current associated with such transient conditions away from the circuit to which the ESD device is connected. Commonly, it is desirable to have the transient current diverted to a low-potential power rail, generally defined as ground. N-type MOS (NMOS) ESDP transistors are often used to achieve that end.
More recently, pluralities of NMOS transistors have been employed in parallel combination to provide protection. However, it is important in such a configuration to make sure that each of the individual transistors making up the composite transistor turns on at substantially the same time. Failure to do so will result in the first of the transistors in the set to turn on to support the entire transient load. That generally causes failure of that transistor unit as well as the entire ESD protection device. Ballast resistance is required in these devices as a means to alleviate problems of non-simultaneous turn-on; however, the ballast that is often required can lead to unacceptable increases in transistor set size. Variations occurring during processing of the prior ballasted ESD devices further tend to yield unreliable ESD protection, particularly where vertical pathways and field oxides were relied upon to provide the resistance. It is well known that such pathways can vary substantially in resistance from one site to another.
One particular ESDP device includes a MOS transistor having its gate coupled to a triggering mechanism. Like the MOS transistor, the trigger is coupled in parallel to the circuit to be protected. The transistor and trigger are designed to operate as follows. The transistor is configured to conduct relatively high currents of the type that may be expected under typical electrostatic conditions, such as those currents associated with human body model spikes. The transistor is also configured to clamp across itself a potential that keeps the circuit to be protected unharmed. A generic representation of the trigger-based ESDP device is shown in FIG. 1. The protected circuit 10 exists between supply pads 20 and 30. An ESD transistor M1 that is typically an N-type MOS transistor, is coupled in parallel with the circuit 10. Finally, a trigger 40 coupled in parallel with the circuit 10 has an output coupled to the gate of M1.
In intended operation, the trigger 40 activates at a desired standoff voltage. The transistor action of transistor M1 thereby clamps the potential applied to circuit 10, preferably at a level and in time to ensure that circuit 10 will not be damaged by the overvoltage event. Ideally, the trigger 40 does not interfere with the standard operation of the circuit 10 when there is no discharge event. It should not turn on too slowly in relation to the discharge event and it should not interfere with the operation of the primary ESD transistor M1. Preferably, the trigger 40 consumes little space on a die and does not cause premature degradation of the entire circuit structure.
Common prior ESDP devices are shown in FIGS. 2 and 3, each of which includes the NMOS primary ESD transistor M1 coupled in parallel with the circuit 10 to be protected. The device of FIG. 2 includes as the trigger an RC gate pump branch formed of a capacitor C1 in series with a resistor R1. The high-potential node of resistor R1 is connected to the gate of M1. The RC branch activates the ESDP transistor M1 by pumping up the potential of its gate to a value beyond the threshold potential. The RC branch effectively lowers the trigger potential of that transistor, and can do so uniformly for a plurality of ESDP transistor elements. That is, transistor M1 turns on before the potential at either of the pads 20 and 30 exceeds a value dangerous for the circuit 10. The transistor M1 thereby diverts current from one pad to the other before damage occurs.
That is the ideal operation of the ESDP device of FIG. 2. However, there are disadvantages associated with the RC branch trigger design. First, as circuits become increasingly smaller and preferably increasingly faster, it is generally undesirable to insert capacitance of the magnitude required for a suitable ESDP device. Second, the additional capacitance may create a pad-to-pad leakage pathway resulting in performance loss, particularly under rapid signal transition conditions. Finally, dependent upon the characteristics of the discharge event, the RC branch may turn on and then turn off before all discharge elements of transistor M1 are fully engaged, while the discharge event remains detrimental to the circuit 10. Alternatively, the pulse may not be long enough to pump up the capacitor C1 enough to reach the threshold gate potential of transistor M1 so as to turn on that transistor and thereby protect the circuit 10.
The second relatively common ESDP device of the prior art is shown in FIG. 3. In that device, the trigger is a Zener diode Z1 that essentially replaces the capacitor C1 of FIG. 2. However, the Zener diode Z1 is preferable when the delay associated with the capacitor charging is undesirable in regard to operation of the circuit 10 to be protected. The Zener diode Z1 is fabricated so as to breakdown at a voltage less than that determined to be suitable for the circuit 10. However, the protection circuit of FIG. 3 may be deficient under certain conditions. Specifically, if the circuit 10 requires a relatively low breakdown potential in order to be protected, and the process-available breakdown voltage and range of the Zener diode Z1 may simply be too high. That may be of particular concern when mixed power supplies (e.g., 5-volt nominal and 3.3-volt nominal supplies are used for coupled circuitry) are involved and multiple voltage protection levels are required. Under certain conditions, the transistor M1 may be turned off if the base drive to the effective internal parasitic lateral bipolar transistor of M1 is insufficient for bipolar action without pumping up the gate potential. Below the Zener diode Z1 breakdown voltage, current produced by Zener breakdown in diode Z1 through R1 falls and the potential at the gate of Ml drops too low to keep it on. Nevertheless, the discharge event may remain and could damage circuit 10. A trigger that fails to remain on when the ESD protection transistor M1 is on, reduces the efficiency of the protective structure and could result in premature loss of current diversion capability of M1.
Therefore, what is needed is an ESD protection circuit that may be fabricated using standard processing methods. Further, what is needed is an ESD protection circuit that remains on during the ESD event conduction process. Still further, what is needed is a triggered ESD protection circuit that may be modified to provide a selectable trigger potential so that ESD protection devices of varying threshold characteristics may be formed as part of a single integrated structure. Yet further, what is needed is a triggered ESD protection circuit that triggers fast enough to divert ESD events of the type that ordinarily occur without reliance on RC dependencies. In effect, what is needed is an ESD protection circuit having a triggering mechanism that continues to charge pump the gate of the ESD transistor throughout the ESD event and has a low on-resistance.
It is an object of the present invention to provide an ESD protection circuit that may be fabricated using standard processing methods. Further, it is an object of the present invention to provide an ESD protection circuit that remains on during the ESD event conduction process. Still further, it is an object of the present invention to provide a triggered ESD protection circuit that may be modified to provide a selectable trigger potential so that ESD protection devices of varying threshold characteristics may be formed as part of a single integrated structure. Yet further, it is an object of the present invention to provide a triggered ESD protection circuit that triggers fast enough to divert ESD events of the type that ordinarily occur without reliance on high capacitance charge pumping or on hot carrier injection. An object of the present invention is to provide an ESD protection circuit having a triggering mechanism that continues to charge pump the gate of the ESD transistor and has a low on-resistance.
These and other objectives are achieved in the present invention by way of an integrated circuit triggering mechanism coupled to the gate of a MOS ESD protection transistor. The triggering mechanism may be any sort of active device, such as a MOS transistor or a bipolar transistor, having an internal gain mechanism. The triggering mechanism has an output coupled to the gate of a conventional MOS ESD protection transistor that is, in turn, coupled in parallel with a circuit to be protected from ESD events. The triggering mechanism, whether a MOS transistor or a bipolar transistor, establishes a voltage lowering condition for the ESD transistor. Specifically, the trigger transistor is designed with a selectable breakdown voltage characteristic. That breakdown voltage must be less than the breakdown voltage of the ESD transistor such that the trigger transistor will turn on first. In addition, that breakdown voltage of the trigger transistor is designed to be more than or equal to a specified standoff voltage. The standoff voltage is the minimum potential at which the ESD protection device must be activated in order to not interfere with normal circuit operation.
While the trigger transistor includes the noted characteristics, its effectiveness is tied to the characteristics of the ESD transistor and the relationship between the two. The ESD transistor of the present invention is preferably designed to carry more current than the trigger transistor can handle. That is, once the trigger transistor sets the ESD protection device of the present invention into an activated state when the standoff voltage is exceeded at a circuit pad, the ESD transistor preferably carries most of the current associated with the ESD event. The ESD transistor is more robust than the trigger transistor to support that current once the ESD transistor is activated. The trigger transistor is the more sensitive of the two and is turned on first so as to generate a current directed to the gate of the ESD transistor. That current flowing through external resistance pumps up the ESD transistor""s gate so that it turns on before the ESD event overloads the circuit to be protected. In turn, the ESD transistor, once on, ensures that the trigger transistor will not be overloaded during the ESD event by absorbing most of the current from that event. This type of ESD device is particularly advantageous when a standoff voltage is required in high speed propagation conditions, or when the ESD device cannot be conducting at potentials below the standoff voltage due to transient premature triggering. The prior RC-triggering systems fail to provide such standoff capability.
The suitable interaction of the trigger transistor and the ESD transistor may be established in a variety of ways. The trigger transistor may be formed with a conduction channel that is shorter than the conduction channel of the ESD transistor. Alternatively, the trigger transistor may be formed with transitional doping in that channel while the ESD transistor is formed without such transitional doping. That transitional doping may be the equivalent of lightly-doped drain (LDD) formation of the type that is often used in MOS transistors to minimize hot electron effects. That transitional LDD doping creates a conduction channel that is effectively narrower in the trigger transistor than it is in the ESD transistor. Of course, that results in a lower breakdown voltage characteristic of that transistor.
It is also preferable to make the trigger transistor smaller than the ESD transistor such that its on-resistance is higher than would be the case if it were sized the same as the ESD transistor while also having the transitional doping. Designing the trigger transistor in the way indicated ensures that it will be activated first by an ESD event and that it will thereby act to pump up the potential of the control node of the ESD transistor prior to the ESD event overloading the circuit to be protected. Once on, the bigger ESD transistor having a larger conduction channel and no transitional doping is capable of conducting more current than can be handled by the trigger transistor. The two transistors therefore work in a synergistic manner to produce a greatly improved ESD protection device.
In operation, the trigger transistor conducts when the potential across its high-potential node and its low-potential node exceeds the designed breakdown potential of that structure. As noted, that breakdown potential is designed into the trigger transistor to be greater than a minimum standoff potential required for standard operation of the circuit to be protected. The current through the trigger transistor is sufficient to produce a potential drop across the control node and bulk of the ESD transistor that is greater than the designed threshold potential of that transistor. It then conducts. The trigger transistor and the ESD transistor are preferably coupled together in a manner such that when both are on, the trigger transistor reduces its contribution to conduction in proportion to their respective on resistance, RON. At high currents, the ESD transistor is designed to have very low RON and takes on most of the conduction load. If the ESD transistor is configured as a MOS transistor and the ESD event current is high enough, the ESD transistor will switch earlier from field effect operation to bipolar transistor breakdown with the aid of the trigger. When that occurs, substantially greater current can be distributed in the well (base) of the effective bipolar transistor in a way that continues to protect the circuit to be protected throughout the entirety of the ESD event.